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Chapter 6: Board Test System
Using the Board Test System
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■
6–11
Write , Read , and Total performance bars—Show the percentage of maximum data
rate that the requested transactions are able to achieve.
Write (MBps) , Read (MBps) , and Total (MBps) —Show the number of bytes of
data analyzed per second.
Error Control
The Error control controls track transaction errors detected during analysis:
■
■
■
■
Detected errors —Displays the number of transaction errors detected in the
hardware.
Inserted errors —Displays the number of errors inserted into the transaction
stream.
Insert Error —Inserts a one-word error into the transaction stream each time you
click the button. Insert Error is only enabled during transaction performance
analysis.
Clear —Resets the Detected Errors and Inserted Errors counters to zeros.
Number of Addresses to Write andRead
The Number of addresses to write andread control determines the number of
addresses to use in each iteration of reads and writes. Valid values range from 2 to
524,288.
Data Type
The Data t ype control specifies the type of data contained in the transactions. The
following data types are available for analysis:
■
■
■
PRBS —Selects pseudo-random bit sequences.
Memory —Selects a generic data pattern stored in the on chip memory of the
Stratix IV GX device.
Math —Selects data generated from a simple math function within the FPGA
fabric.
Read and Write Control
The Read and write control control specifies the type of transactions to analyze. The
following transaction types are available for analysis:
■
■
■
Write then read —Selects read and write transactions for analysis.
Read only —Selects read transactions for analysis.
Write only —Selects write transactions for analysis.
The QDRII+ Tab
The QDRII+ tab allows you to read and write the QDR II+ memory on your board
and independently test each QDR II+ port. Figure 6–6 shows the QDRII+ tab.
? November 2009
Altera Corporation
Audio Video Development Kit, Stratix IV GX Edition User Guide
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